Dedicated image processing architecture is needed to meet end-user requirements
End user demand is to get DSC quality out of a smaller size phone. The camera ISP is more and more implemented on the baseband or application processor in the phone, in order to benefit from the state of the art 40nm or 28nm manufacturing process used in these chips which reduces silicon cost compared to discrete chip or less dense sensor process.
However, new sensor technologies which are updated every year require changes in the ISP to keep the required image quality by adapting to the new pixels characteristics. Also new imaging features are needed at an increasing pace to meet user demand and differentiate on the competitive smartphone market.
However, the time between the specification freeze of the baseband and application processor and its availability in a phone can be several years. The ability to change features without silicon respin is therefore mandatory. A fully hardwired ISP does not meet the end user requirements under these circumstances.
The computing power needed to process 1080p video in real time at 30fps or 60fps is one to two orders of magnitude higher than what the main ARM processor, a DSP or a GPU can deliver. A dedicated low power scalable image processing architecture compatible with HD video recording is therefore required.
DxO IPC provides the flexibility to meet end-user needs
DxO Imaging Programmable Core (DxO IPC) is based on DxO Labs’ programmable SIMD core dedicated to image processing. It allows quick and easy enriching of your image and video processing chain with advanced imaging technologies for a low silicon and power consumption cost.
DxO IPC allows fast implementation of high-quality video and still images features with significant processing requirements, such as:
Features are available from DxO Labs, from partners, or they can be your own implementation. Since these features need to either run at video frame rate, or process several million pixels, the processing requirements are too high for a standard DSP. DxO IPC is dedicated to imaging, making it much more silicon- and power-efficient for this class of algorithms.
DxO IPC is a silicon-proven architecture shipping in high-volume consumer applications today.
DxO Labs delivers:
A configurable, scalable, and programmable SIMD silicon IP core optimized for image processing with multi-thread capabilities;
A full-feature programming tool that includes DxO IRIS high-level language dedicated to imaging (code size 95% smaller than C) and associated compiler for automatic generation of both a bit-exact C-model and the embedded microcode;
A complete SDK that runs on any ARM processor, with support for multiple use cases and configurations.
DxO IPC’s flexible and programmable architecture safeguards your silicon investment and allows you to implement advanced features in a very short time.
DxO IPC in your system
DxO IPC provides the ideal solution:
For extending your imaging chain without risk;
For quickly developing or integrating sophisticated new features (from DxO Labs, from partners, or your own) without any silicon changes;
For upgrading your imaging features over-the-air.
Contact us for more information